Hakduran Koc

Research

 

System Design Laboratory (SDL) located at D132 is supervised by Dr. Koc. The main research areas are given below. Students interested in joining SDL are strongly encouraged to take Dr. Koc's courses.

Main research areas include Embedded Systems, Computer Architecture and Multi-core Architectures. More specifically:

  • Performance Improvements in Multi-Processor Systems
  • Memory Space Minimization of Data-Intensive Applications
  • Energy/Power Optimizations in Embedded Systems
  • Reliability Improvements in Digital Systems
  • Implementing Primitive Human Body Movements in Robotics Environments at Real-time
  • Non-Uniform Cache Architectures (NUCA)
  • High Level Synthesis

 

Funded Research Grants

  • Hakduran Koc (PI); “I/O Processing for Cyber Physical Systems Using Scratch Pad Memory”; Sponsor: UHCL FRSF; Period: 10/2015 – 10/2016.
  • Hakduran Koc (PI); “Improving Performance and Energy Consumption through Path-Based Hardware/Software Partitioning”; Sponsor: Lekkos Endowment; Period: 7/2015 – 6/2016.
  • Hakduran Koc (PI); “Energy and Reliability Improvements in Many-Core Embedded Systems using Fault Propagation Scope”; Sponsor: UHCL FRSF; Period: 5/2014 – 4/2015.
  • Hakduran Koc (PI); “Integrating Parallel and Distributed Computing Topics into UHCL Computer Engineering Undergraduate Curriculum”; NSF/IEEE-TCPP CDER Center; July 2013, multi-semester. (educational grant)
  • Hakduran Koc (PI); “Improving Reliability through Task Recomputation in Heterogeneous Multi-Core Architectures”; Sponsor: UHCL FRSF; Period: 5/2013 – 4/2014.
  • Hakduran Koc (PI); “Real-Time Wireless Transfer and Implementation of Primitive Human Body Movements to Robotics Environments – Phase 1”; Sponsor: Texas Fortune Inc.; Period: 1/2013 – 1/2014.
  • Hakduran Koc (PI); “Reducing Energy Consumption in Single-Core Embedded Systems Using Data Recomputation”; Sponsor: UHCL FRSF; Period: 11/2011 – 10/2012.

Thanks to our sponsors for their financial support!

 

Description of Research Areas

Performance Improvements in Chip Multi-Processors
Recent advances in process technologies of integrated circuits provide the opportunity of putting millions of transistors on a single die. This enables designers to place multiple CPUs on a single chip. Even though the current approaches are quite effective for single-processor based systems, they are not applicable, in many cases, to multi-cores and have to be revisited to effectively utilize the benefits of chip multi-processors (CMP). In recent years, researchers have directed their attention to on-chip memory components such as Scratch Pad Memory (SPM) in addition to hardware-controlled on-chip caches to be able to meet very tight constraints, especially in embedded systems. SPM is a software-managed on-chip SRAM with guaranteed fast access time. The advantages of SPM include power/energy efficiency, reduced cost, better performance, and real-time predictability.

Minimization of Memory Space Consumption in Data-Intensive Applications
Memory space consumption is an important metric to optimize for embedded designs with tight memory constraints. While this is certainly true for both code and data memory, the rate at which the data sizes of embedded applications increase far exceeds the rate at which their code sizes increase. As embedded applications are processing increasingly larger data sets, keeping their memory space consumptions under control is becoming a very pressing issue. As a result, optimizing for data memory size is becoming increasingly more important than optimizing for code memory size. Observing this, several prior efforts have considered memory space reduction techniques (in both hardware and software) based on data compression and lifetime based memory recycling.

Energy/Power Optimizations in Embedded Systems
Energy/power concerns are becoming increasingly critical in computing systems. Especially in mobile embedded systems, the functionality of a device is directly proportional to its battery life. The energy is primarily consumed in on-chip components and off-chip memory. On-chip cache memories account for up to 50% of total on-chip energy consumed in these systems. The energy consumption of off-chip memory constitutes a significant portion of the total energy budget. On the other hand, in Deep Sub Micron technologies, the significant portion of the energy is dissipated as leakage even though the components are idle. This leakage energy is more severe in memories. Consequently, memories have gathered much attention by researchers in order to improve the energy/power consumption of computing systems.

Reliability Improvements in Digital Systems
In the past, researchers put significant effort in order to maximize performance of computing systems; and later, to optimize the energy/power consumption. Given that erroneous results generated by super-fast and power-aware architectures have no meaning, reliability has gathered much attention by researchers in recent years. In the literature, numerous hardware and software-based techniques have been proposed (depending on the source of the failure such as transient soft errors or permanent failures) in order to make components/systems more dependable. Reliability is one of the most important optimization metrics in any computing platform. In order to improve reliability of a system, we target at incorporating various high-level techniques during synthesis of digital systems without affecting the performance or area (or with an acceptable/allowed degradation).

Implementing Primitive Human Body Movements in Robotics Environments at Real-time
Robots were first utilized in the industry for various purposes as programmable machines to perform a set of pre-specified tasks without interacting with humans in the course of operation. However, in recent years, significant efforts have been reported in the literature for human-robot interactions. In systems where humans and robots interact during the execution of a task, robots do not perform preprogrammed tasks, but execute different sets of actions depending on the commands sent by humans. Our goal is to investigate various ways to transfer human body movements to robotics environments in real-time. Our robot architecture consists of electrical and mechanical components such as microcontrollers, motors, mechanical structures, etc. to perform the desired movements. In order to prevent any physical connection between two parties, we implement a wireless connection to transfer the commands from human to robot. In the target system, the signals representing body movements are either detected by sensors attached to body (in case of arm movements) or generated by a human (in case of leg movements). In the final prototype, energy consumption and speed are two important optimization metrics to consider during the design process.

Non-Uniform Cache Architectures
Driven by the increase in data sizes of applications, today’s high-end computing systems intent to have large on-chip memories in order to prevent the performance degradation caused by the high access latency of off-chip memory. Current process technology with smaller feature sizes allows us to place large L2 caches on chip. However, some cache lines in this configuration may experience different access latencies due to dominating on-chip communication delay and add new levels into memory hierarchy. Such L2 organizations are referred to as Non-Uniform Cache Architectures (NUCAs). Recently, there has been some research on data placement for NUCAs in the context of chip multi-processors.