To bridge the gap between industry needs and academia, an investigation on the specific requirements for an entry-level chip designer is conducted, including the FPGA Hardware Engineer from Mentor Graphics, Digital Integrated Circuit Design (PHY) Engineer from Apple, Design Verification Engineer from AMD, and many more. The research is based on the information on Indeed.com and Linkedin.com by filtering the relevance of full-time job type and entry-level experience. After compiling the details of 20 posted job opportunities, the key qualifications needed are summarized in (ToE2021) You are free to use these open sources as long as you follow the copyright (cite the original source and authors.) Any question, please feel free to contact yangxia@uhcl.edu

UNIX/LINUX command Editor such as VIM/EMacs/WinEdt Simulator such as ModelSim/VCS/NC FPGA tools such as Vivado/Quartus Scripts such as makefile/tcl/csh/perl Verilog/VHDL Language System Verilog based on OOP Fundamental of dsign and testbench with bus function models (BFM) and scoreboard Fundamental of verification methods including constrain-random test, coverage, and assertion Verification methodology such as UVM or VMM Knowledge of bus architecture and protocols such as AMBA AXI, I2C/SPI/SDIO/UART/GPIO, and some algorithms

The Difference between implementation of Level sensitive and Edge Sensitive sequential circuits The Difference between asynchronous and synchronous reset The Difference between non-blocking and blocking design The Difference between Reg and Net in Verilog HDL What is the synthesis results with incomplete if-else and case with Verilog HDL Given Verilog code, draw the synthesis results

What are the setup and hold timing issues? How to caculate the maximum operational frequency? Is it possible to have zero skew in our design? What is the cricitcal path? How to process the issue of clock domain crossing? How to process the issue of time violation?

Design AND and OR gates using 2:1 MUX Design counter with Verilog/VHDL Explain FSM with Verilog HDL Verilog/VHDL code of a Latch and DFF Verilog/VHDL code of a FSM Verilog/VHDL code of tri-stage buffer/latch/mux Asynchronous FIFO Design Experience on design of simple SoC interfaces like I2C/SPI/SDIO/UART/GPIO Experience on design of simple bus protocol like DMA/Memory Controller/Bridges Experience on design of simple algorithms like Video/Audio processing

What is OOP? What is constrain-random tests? What is assertion? What is coverage? What is UVM/VMM?

What is the difference between ASIC and FPGA design? What is HLS? Experience on design of ARM-FPGA combined syst. such as Zync and UltraScale SoC