Open Projects

Introduction:

OpenIC platform was created by Professor Xiaokun Yang on Nov. 11, 2018, aiming at serving research and teaching courses at UHCL and other universities, as well as to bring together researchers and students in colleges and high schools with interests in Integrated Circuit design. The main goal of OpenIC is to bridge the gap between academia and industry needs. You are free to use these open sources as long as you follow the copyright (cite the original source and authors.) Any question, please feel free to contact yangxia@uhcl.edu.

Parameterizable Design and Verification on CNN Neural Networks with Chisel HCL:

Description: TBA Author: Vega, Mario, Date: Jan. 2022

Parameterizable Design on MLP Neural Networks with Chisel HCL:

Description: TBA Author: Madineni, Mukesh Chowdary, Date: Jan. 2022

Accelerating Neural Networks on An Autonomous Robot Platform:

Description: The need for autonomous vehicles is rapidly increasing in today's world. Apart from the vehicle manufacturing organizations, a few semiconductor vendors such as Intel and AMD/Xilinx are also investing in the development of application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and system-on-chips (SoCs) in the field of hardware acceleration and control to vehicle automation. Therefore, this project will explore the FPGA acceleration with Deep Neural Networks on a hardware platform of an autonomous driving robot car. The experimental system is mainly composed of a Xilinx PYNQ-Z2 board as a computing device, a USB camera as the image/video sensor, and a computer to view the results. The main applications in image/video detection and recognition of traffic signs, obstacles, and comparison of execution time between FPGA and software will be performed in this work. Compared with the software implementation, the results of FPGA acceleration show a 2957× speedup to the single road sign recognition using Binarized Neural Networks (BNNs) and 17% latency reduction to the object detection using Quantized Neural Networks (QNNs). The final goal of this project is to demonstration of a smart system with PYNQ FPGA, capable of accelerating the self-driving relevant algorithms within the time constraints. Capstone Reference: (PDF) Author: Sarala K Surapally, Date: May. 2021

A Low-cost and High-speed Convolotional Neural Network Design with FPGA:

Description: This project proposes field-programmable gate array (FPGA) acceleration on a scalable multi-layer perceptron (MLP) neural network (NN) for classifying handwritten digits. First, an investigation to the network architectures is conducted to find the optimal FPGA design corresponding to different classification rates. As a case study, then a specific single-hidden-layer MLP network is implemented with an eight-stage pipelined structure on Xilinx Ultrascale FPGA. It mainly contains a timing controller designed by Verilog Hardware Description Language (HDL) and sigmoid neurons integrated by Xilinx IPs. Finally, experimental results show a greater than x10 speedup compared with prior implementations. The proposed FPGA architecture is expandable to other specifications on different accuracy (up to 95.82%) and hardware cost. Paper Reference: (PDF) Thesis Reference: (PDF) Author: Isaac Westby, Date: Aug. 2020

An Open Audio Processing Platform with Zync FPGA:

Description: This projects presents an open audio processing platform on Zync7000 Field-Programmable Gate Array (FPGA), capable of collecting analog frequency signal through a microphone, and pushing out a data set of frequencies and amplitudes to a UART interface. The design can be programmed on Vivado Paper Reference: ISVLSI 2019 / [Ref] and ISMCR 2019 / [Ref] Open Tutorial: Audio Processing Platform with Zync Author: Kevin Vaca and Prof. Xiaokun Yang, Date: Sept. 2019

A Scalable Image/Video Processing Platform with Nexys 4 FPGA:

Description: This project presents an image/video processing platform, enabling to capture frames of images by interfacing a low-cost OV7670 camera and in real time display both the original images and the results of processed images on a VGA-interfaced monitor. Specifically we presents our framework able to simultaneously display up to four 320x240 images in a 640x480 window, capable of showing the in-process images, the final results of the images, as well as the original images through the VGA interface. As a case study, we design a simple color to binary converter with two submodules - color to grayscale converter and then grayscale to binary converter. We demonstrate the validity of showing all the original color images captured from the OV7670 camera, the inter-process grayscale images, and the final binary images in different regions via the VGA master. The Design-Under-Test (DUT) was written by Verilog HDL and tested on the Nexys 4 FPGA, and the verification environment can be automatically run on ModelSim-Intel FPGA Starter Edition and programmed on Vivado Paper Reference: ISQED 2019 / [Ref] Open Source Code: Image/Video Processing Platform , or you can find the source code on GitHub/xiaokunyang Author: Yunxiang Zhang and Prof. Xiaokun Yang, Date: Aug. 2018

AES Core:

Description: This open source design contains the design-under-test (DUT) of AES core, testbench, and a tcl script. The simulator is ModelSim-Intel FPGA Starter Edition. Paper Reference: ACM JETC 2017 / [Ref] and ASP-DAC 2017 / [Ref] Open Source Code: AES Engine and Simlation Env Author: Prof. Xiaokun Yang, Date: Sept. 2017